The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, the present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
Memory cells of DRAM are placed at intersections between a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. One memory cell comprises a MISFET (Metal Insulator Semiconductor Field Effect Transistor) for selecting a memory cell and a data storage capacitor connected in series to the MISFET.
The MISFET for selecting a memory cell is formed in an active region surrounded by a device isolation region, and is mainly composed of a gate insulating film, a gate electrode combined with a word line, and a pair of semiconductor regions constituting a source and a drain. Typically, two MISFETs for selecting a memory cell are formed in each of the active regions, and these two MISFETs have a common source or a common drain (semiconductor region) at the center of the active region.
The bit line is arranged on the MISFET for selecting a memory cell and is electrically connected to one (the common semiconductor region which the two MISFETs share) of the source and drain (semiconductor regions) via a connection hole in which a plug made of polycrystalline silicon or the like is buried. Also, the data storage capacitor is arranged on the bit line and is electrically connected to the other of the source and drain (semiconductor regions) of the MISFET for selecting a memory cell via a connection hole in which a plug made of polycrystalline silicon or the like is buried.
As described above, as measures for compensating the reduction in stored charge due to the scaling down of a memory cell, a stacked capacitor structure is adopted in the recent DRAM, in which a data storage capacitor is arranged on a bit line.
However, in the case of a large capacity DRAM with a capacity more than 256 megabit in which the scaling down of a memory cell is further promoted, it is considered that only the adoption of the stacked capacitor structure cannot sufficiently compensate the reduction in the stored charge. Thus, the introduction of a high dielectric material such as tantalum oxide (Ta2O5) as a capacitor insulating film of the data storage capacitor has been developed.
However, the high relative dielectric constant cannot be obtained even by simply depositing the above-mentioned high dielectric material such as tantalum oxide, and the leak current of the film is large. Therefore, the crystallization of the film and the improvement of the film quality by means of the thermal treatment in a high-temperature oxygen atmosphere at 750xc2x0 C. to 800xc2x0 C. are required after forming the film. However, the thermal treatment in such a high temperature causes a problem of characteristic variation in the MISFET.
For its prevention, in the case where the high dielectric material is used to form a capacitor insulating film, platinum group metal, for example, Ru (ruthenium) is used as a lower electrode serving as an underlayer of the insulating film. The reason thereof is as follows. That is, in the case where a high dielectric film is deposited on a surface of a platinum group metal, the crystallization of the film and the improvement of the film quality can be achieved by the low-temperature thermal treatment at 700xc2x0 C. or lower. Therefore, the total amount of heat applied in the thermal treatment in the entire manufacturing process can be reduced, and thus, the characteristic variation in the MISFET can be prevented.
Meanwhile, in the case where the above-mentioned platinum group metal is used as the material of the lower electrode, since the platinum group metal is an oxygen permeable material, oxygen permeates through the high dielectric film and the lower electrode and reaches the silicon plug below them if the thermal treatment is performed in the oxygen atmosphere after forming the high dielectric film on the surface of the lower electrode. As a result, the platinum group metal and the silicon are reacted to form a high-resistance layer made of metal silicide at the interface therebetween.
For the solution of the above-mentioned problem, a method in which a barrier layer for preventing the reaction between the lower electrode made of the platinum group metal and the silicon plug is formed therebetween has been proposed.
The Japanese Patent Laid-Open No. 10-79481 proposes a conductive layer (metal silicon nitride layer) as a barrier layer, which contains refractory metal such as Ti (titanium), W (tungsten), Ta (tantalum), Co (cobalt), and Mo (molybdenum), silicon, and nitrogen. Such a conductive layer is provided for the purpose of avoiding such disadvantages that a metal silicide layer is formed by mutual diffusion of platinum group metal and silicon due to a thermal treatment at 700xc2x0 C. to 800xc2x0 C. performed in the reflow and planarization of a silicon oxide film, and that the metal silicide layer is oxidized to form a silicon oxide layer with small dielectric constant. In the invention, the barrier layer is preferably formed by laminating a first layer containing columnar crystal or amorphous and a second layer containing granular crystals. Also, a layer containing Ti is preferably formed between the barrier layer and a silicon plug for improving the adhesion therebetween.
The Japanese Patent Laid-Open No. 10-209394 points out the problems as follows. That is, in such a case where a dielectric film formed on a lower electrode and a silicon plug below the lower electrode are contacted to each other due to the mask misalignment when forming the lower electrode on a connection hole in which the silicon plug is buried, the reaction between oxygen in the dielectric film and silicon is caused. As a result, a high-resistance silicon oxide film is formed and the leak current in the dielectric film is increased due to the shortage of oxygen. For the solution of the problems, the gazette proposes to form a blocking film made of silicon nitride between the dielectric film and the silicon plug.
The Japanese Patent Laid-Open No. 11-307736 relates to a ferroelectric memory and discloses a technique in which a tantalum silicon nitride (TaSiN) film as a diffusion barrier layer is formed on a silicon plug and an Ir film as an oxygen blocking film is formed on the diffusion barrier film when forming a capacitor composed of a lower electrode made of iridium oxide (IrOx), a dielectric film made of ferroelectric substance such as PZT (lead zirconate titanate), and an upper electrode made of platinum group metal such as Pt on the silicon plug.
As described above, in the conventional technique, a barrier layer provided between a lower electrode of a capacitor and a silicon plug functions to prevent the formation of a high-resistance oxide film on a surface of the silicon plug at the time when a thermal treatment of a capacitor insulating film made of high dielectric substance formed on the lower electrode is performed in an oxygen atmosphere.
However, with the further scaling down of the memory cell, the diameter of a through hole in which a silicon plug is buried is reduced, and a surface area of a barrier layer formed on the silicon plug is also reduced. As a result, when ,performing a thermal treatment of a high dielectric film on a lower electrode in an oxygen-containing atmosphere, the contact resistance between the lower electrode and the silicon plug is increased due to the extremely small surface area of the silicon plug even in the case where an oxide layer formed on the surface of the barrier layer is extremely thin. Consequently, a conduction failure may be caused in an extreme case.
An object of the present invention is to provide a technique for preventing a conduction failure between a lower electrode and a silicon plug caused by a thermal treatment of a dielectric/film formed on a lower electrode of a capacitor.
The above and other objects and novel characteristics of the present invention will be apparent from the description and the accompanying drawings of this specification.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
An aspect of a semiconductor integrated circuit device according to the present invention is a DRAM, which is provided with: a first insulating film formed over a main surface of a semiconductor substrate and having a first connection hole in which a first conductive layer is buried; a second insulating film formed on the first insulating film and having a trench over the first connection hole; and a capacitor formed in the trench, wherein the capacitor comprises a lower electrode constituted by a second conductive layer formed on a sidewall and bottom surface of the trench, a capacitor insulating film formed on the lower electrode, and an upper electrode constituted by a third conductive layer formed on the capacitor insulating film, and a metal silicide layer electrically connected to the first conductive layer in the first connection hole is provided between the sidewall and bottom surface of the trench and the lower electrode.
A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of: (a) forming a first connection hole in an first insulating film formed over a main surface of a semiconductor substrate, and burying a first conductive layer in the first connection hole; (b) forming a second insulating film on the first insulating film, and forming a trench in the second insulating film over the first connection hole; (c) forming a metal silicide layer on a sidewall and bottom surface of the trench, the metal silicide layer being electrically connected to the first conductive layer in the first connection hole; (d) forming a lower electrode of a capacitor on the metal silicide layer; (e) forming a capacitor insulating film of the capacitor on the lower electrode; and (f) forming an upper electrode of the capacitor on the capacitor insulating film.